This application claims priority to Korean Patent Application No. 2005-48823, filed on Jun. 8, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to image sensors, and more particularly, to pixel circuits of a complementary metal oxide semiconductor (CMOS) image sensor having shared components.
2. Description of the Related Art
Complementary metal oxide semiconductor (CMOS) image sensors are included in common electronic devices such as mobile phones and digital still cameras for example. CMOS image sensors convert images into electrical signals, convert the electrical signals into digital image signals, and output the digital image signals. Such digital image signals are commonly output as three-color (red, green, and blue) image data signals. After being processed, the digital image signals drive display devices such as liquid crystal displays (LCDs).
FIG. 1 is a block diagram of a conventional CMOS image sensor 100. Referring to FIG. 1, the image sensor 100 includes an active pixel sensor (APS) array 110, a row driver 120, and an analog-to-digital converter (ADC) 130.
The row driver 120 receives a control signal from a row decoder (not shown), and the ADC 130 receives a control signal from a column decoder (not shown). The image sensor 100 also includes a controller (not shown) that generates timing control signals as well as addressing signals for outputting a selected image signal as detected by each pixel.
FIG. 2 illustrates an example of a color filter pattern of the APS array 110 of FIG. 1. Referring to FIG. 2, the CMOS image sensor 100, if it is a color image sensor, includes a color filter in an upper part of each pixel to process light of a certain color. The CMOS image sensor 100 includes at least three types of color filters to generate color signals. The most common color filter pattern is a Bayer pattern in which patterns of red and green and patterns of green and blue are repeated in alternate rows. In this case, green, which is closely related to a luminance signal, is placed in all rows, and red and blue are placed in alternate rows to enhance luminance resolution. CMOS image sensors including more than one million pixels are implemented in, for example, digital still cameras, to enhance resolution.
The APS array 110 included in the CMOS image sensor 100 having this pixel structure includes photodiodes. Each photodiode detects light for converting the detected light into an electrical signal which is the image signal. The analog image signal output from the APS array 110 is for one of the three-colors (red, green, and blue). The ADC 130 receives and then converts the analog image signal output from the APS array 110 into a digital signal using a well-known correlated double sampling (CDS) method.
FIG. 3 is a circuit diagram of a pixel driving circuit 300 of the APS array 110 of FIG. 1. Unit pixel circuits 310 and 320 are arranged two-dimensionally in the APS array 110, and each of the unit pixel circuits 310 and 320 includes a photodiode PD and three transistors. Although not shown in FIG. 3, unit pixel circuits including four transistors may be used. The unit pixel circuits 310 and 320 perform a rolling shutter mode operation, i.e., a continuous frame capture mode operation, using the CDS method.
For a selected pixel, a floating diffusion (FD) node signal is generated and output as a reset signal VRES from the signals RX, DRN, and VDD turning on a reset transistor and a source follower transistor. Additionally for the selected pixel, a signal detected by the photodiode PD is transmitted to the FD node when a transfer control signal TX becomes active, and an image signal VSIG incorporating such a detected signal is output by the source follower transistor.
The difference between the reset signal VRES and the image signal VSIG, which is an analog signal, is converted by the ADC 130 into a digital signal. The signals DRN, VDD, RX, and TX may be generated by the row driver 120. In this manner in FIG. 3, each of the unit pixel circuits 310 and 320 included in the CMOS image sensor 100 includes the photodiode PD and the transistors for outputting the reset signal VRES and the image signal VSIG using appropriate timing.
Recently, as the number of pixels that is included in an image sensor has increased, smaller size pixels are desired for enhancing display quality with higher pixel density. Thus, the size of photodiode PD and the transistors of the unit pixel circuits 310 and 320 and the metal wiring connecting the photodiode PD and the transistors are desired to be designed accordingly.
In particular, sufficient space is desired for the photodiode PD in each of the unit pixel circuits 310 and 320. To this end, the number of transistors in each of the unit pixel circuits 310 and 320 may be reduced. Also, attempts are being made to reduce the size of the transistors in each of the unit pixel circuits 310 and 320 using advanced fabrication technology for an enhanced fill factor of the photodiode PD. However, there is a limit to reducing the number of transistors in each of the unit pixel circuits 310 and 320, and advanced fabrication technology is expensive. These problems are exacerbated when an additional transistor is needed for removing overflow current from the photodiode PD for a global shutter mode operation, i.e., a signal frame capture mode operation.
To enhance external light reaching the photodiode PD, the widths of metal wiring in an upper layer of the photodiode PD may be reduced. Such metal wiring is a major obstruction in an optical path. However, there is a limit to reducing the widths of metal wiring while complying with design rules.